1. Field of the Invention
The invention relates generally to timing systems and more particularly to signal pattern generation systems for generating a series of multiple signal patterns and to event recording systems for recording the time at which digital trigger signals are asserted by an external system.
2. Description of the Related Art
Processor based control systems are well known which produce digital output signal patterns used to control external systems such as test and measurement equipment. Frequently, individual digital output signals must be asserted at different times. Consequently, in the past there have been timing systems for ascertaining the different times at which different digital output signals are to be asserted. Typically, such timing systems included mechanisms to continuously provide a measure of elapsed time and typically, such timing systems included mechanisms to continuously provide a measure of elapsed time and mechanisms to generate individual digital output signals at appropriate times.
Processor-based monitoring systems also are well known for monitoring the assertion of one or more digital trigger signals by an external system. The external system, for example, may assert different digital trigger signals to indicate the occurrence of different events such as, the beginning or end of measurements of a device under test or a time interval during which data is taken. Since the time at which events occur relative to the occurrence of other events often is of interest, such prior timing systems frequently included mechanisms to substantially continuously provide a measure of elapsed time and mechanisms to record the times at which different trigger signals are asserted by the external system.
While earlier timing systems for use in conjunction with control and/or monitoring systems generally have been acceptable, there have been shortcomings with their use. For example, the time at which a trigger signal is asserted may depend upon the time at which a digital output signal was asserted, and the measure of delay between the two signals may be of interest. More specifically, for example, an output signal may cause the external system to provide a stimulus to a device under test, and the external system may assert the trigger signal when the response of the device to the stimulus reaches a prescribed threshold. The delay between the stimulus-provoking output signal and the responsive trigger signal may represent a measure of the response time of the device under test to the stimulus. Unfortunately, a lack of synchronization between the mechanisms used to provide a measure of elapsed time in timing systems used to produce output signals and corresponding mechanisms used in timing systems used to record assertions of trigger signals can lead to inaccuracies in measurement of such response time. Thus, there has been a need for close synchronization of the mechanisms used in timing systems to provide measurements of elapsed time for use by control systems and monitoring systems. The present invention meets this need.
Furthermore, earlier timing systems used in conjunction with control systems often have included relatively extensive circuitry to ascertain the time when individual digital output signals in a multiple signal pattern are to be asserted. For example, there have been timing systems in which a separate multiple bit register and a corresponding separate multiple bit comparator is employed for each output terminal on which a digital output signal can be asserted. In operation, for each output terminal, a register stores a multiple bit binary value that represents the clock value at the time when a digital output signal is to be generated. Moreover, for each such output terminal, a corresponding comparator compares the multiple bit binary value stored in the corresponding register with a clock count. When a match between register value and clock count occurs, a processor within the control system is interrupted so that it can generate an appropriate digital output signal on the output terminal.
Unfortunately, the implementation of such multiple comparators and multiple registers involves the use of a significant amount of circuitry. Additionally, the use of interrupts to involve the processor in the generation of digital output signals each time a match occurs on any one of multiple output terminals often can result in inefficient use of processor time. Thus, there has been a need for a timing system that permits the use of fewer comparators and fewer registers and which permits more efficient use of processor time. The present invention also meets these needs.